mii/qemu
1
0
Fork 0
mirror of https://github.com/mii443/qemu.git synced 2025-08-24 16:09:37 +00:00
Code Issues Packages Projects Releases Wiki Activity

target-mips: Misaligned memory accesses for R6

Browse Source 
Release 6 requires misaligned memory access support for all ordinary memory
access instructions (for example, LW/SW, LWC1/SWC1).
However misaligned support is not provided for certain special memory accesses
such as atomics (for example, LL/SC).

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
This commit is contained in:
Yongbok Kim
2015-06-01 12:13:22 +01:00
committed by Leon Alrae
parent 71c199c81d
commit be3a8c53b4
2 changed files with 28 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
target-mips/translate_init.c
View File

@ -607,7 +607,7 @@ static const mips_def_t mips_defs[] =
},
{
/* A generic CPU supporting MIPS64 Release 6 ISA.
FIXME: Support IEEE 754-2008 FP and misaligned memory accesses.
FIXME: Support IEEE 754-2008 FP.
Eventually this should be replaced by a real CPU model. */
.name = "MIPS64R6-generic",
.CP0_PRid = 0x00010000,