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target/i386: use TSTEQ/TSTNE to check flags

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The new conditions obviously come in handy when testing individual bits
of EFLAGS, and they make it possible to remove the .mask field of
CCPrepare.

Lowering to shift+and is done by the optimizer if necessary.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
2023-10-27 04:17:09 +02:00
parent 395d5d09c7
commit af87044127
1 changed files with 16 additions and 16 deletions
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32
target/i386/tcg/translate.c
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@ -995,8 +995,8 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
case CC_OP_EFLAGS: case CC_OP_EFLAGS:
case CC_OP_SARB ... CC_OP_SARQ: case CC_OP_SARB ... CC_OP_SARQ:
/* CC_SRC & 1 */ /* CC_SRC & 1 */
return (CCPrepare) { .cond = TCG_COND_NE, return (CCPrepare) { .cond = TCG_COND_TSTNE,
.reg = cpu_cc_src, .mask = CC_C }; .reg = cpu_cc_src, .mask = -1, .imm = CC_C };
default: default:
/* The need to compute only C from CC_OP_DYNAMIC is important /* The need to compute only C from CC_OP_DYNAMIC is important
@ -1013,8 +1013,8 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
static CCPrepare gen_prepare_eflags_p(DisasContext *s, TCGv reg) static CCPrepare gen_prepare_eflags_p(DisasContext *s, TCGv reg)
{ {
gen_compute_eflags(s); gen_compute_eflags(s);
return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, return (CCPrepare) { .cond = TCG_COND_TSTNE, .reg = cpu_cc_src,
.mask = CC_P }; .mask = -1, .imm = CC_P };
} }
/* compute eflags.S to reg */ /* compute eflags.S to reg */
@ -1028,8 +1028,8 @@ static CCPrepare gen_prepare_eflags_s(DisasContext *s, TCGv reg)
case CC_OP_ADCX: case CC_OP_ADCX:
case CC_OP_ADOX: case CC_OP_ADOX:
case CC_OP_ADCOX: case CC_OP_ADCOX:
return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, return (CCPrepare) { .cond = TCG_COND_TSTNE, .reg = cpu_cc_src,
.mask = CC_S }; .mask = -1, .imm = CC_S };
case CC_OP_CLR: case CC_OP_CLR:
case CC_OP_POPCNT: case CC_OP_POPCNT:
return (CCPrepare) { .cond = TCG_COND_NEVER, .mask = -1 }; return (CCPrepare) { .cond = TCG_COND_NEVER, .mask = -1 };
@ -1057,8 +1057,8 @@ static CCPrepare gen_prepare_eflags_o(DisasContext *s, TCGv reg)
.reg = cpu_cc_src, .mask = -1 }; .reg = cpu_cc_src, .mask = -1 };
default: default:
gen_compute_eflags(s); gen_compute_eflags(s);
return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, return (CCPrepare) { .cond = TCG_COND_TSTNE, .reg = cpu_cc_src,
.mask = CC_O }; .mask = -1, .imm = CC_O };
} }
} }
@ -1073,8 +1073,8 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg)
case CC_OP_ADCX: case CC_OP_ADCX:
case CC_OP_ADOX: case CC_OP_ADOX:
case CC_OP_ADCOX: case CC_OP_ADCOX:
return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, return (CCPrepare) { .cond = TCG_COND_TSTNE, .reg = cpu_cc_src,
.mask = CC_Z }; .mask = -1, .imm = CC_Z };
case CC_OP_CLR: case CC_OP_CLR:
return (CCPrepare) { .cond = TCG_COND_ALWAYS, .mask = -1 }; return (CCPrepare) { .cond = TCG_COND_ALWAYS, .mask = -1 };
case CC_OP_POPCNT: case CC_OP_POPCNT:
@ -1152,8 +1152,8 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
break; break;
case JCC_BE: case JCC_BE:
gen_compute_eflags(s); gen_compute_eflags(s);
cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, cc = (CCPrepare) { .cond = TCG_COND_TSTNE, .reg = cpu_cc_src,
.mask = CC_Z | CC_C }; .mask = -1, .imm = CC_Z | CC_C };
break; break;
case JCC_S: case JCC_S:
cc = gen_prepare_eflags_s(s, reg); cc = gen_prepare_eflags_s(s, reg);
@ -1167,8 +1167,8 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
reg = s->tmp0; reg = s->tmp0;
} }
tcg_gen_addi_tl(reg, cpu_cc_src, CC_O - CC_S); tcg_gen_addi_tl(reg, cpu_cc_src, CC_O - CC_S);
cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = reg, cc = (CCPrepare) { .cond = TCG_COND_TSTNE, .reg = reg,
.mask = CC_O }; .mask = -1, .imm = CC_O };
break; break;
default: default:
case JCC_LE: case JCC_LE:
@ -1177,8 +1177,8 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
reg = s->tmp0; reg = s->tmp0;
} }
tcg_gen_addi_tl(reg, cpu_cc_src, CC_O - CC_S); tcg_gen_addi_tl(reg, cpu_cc_src, CC_O - CC_S);
cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = reg, cc = (CCPrepare) { .cond = TCG_COND_TSTNE, .reg = reg,
.mask = CC_O | CC_Z }; .mask = -1, .imm = CC_O | CC_Z };
break; break;
} }
break; break;