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memory: Single byte swap along the I/O path
Now that MemOp has been pushed down into the memory API, and callers are encoding endianness, we can collapse byte swaps along the I/O path into the accelerator and target independent adjust_endianness. Collapsing byte swaps along the I/O path enables additional endian inversion logic, e.g. SPARC64 Invert Endian TTE bit, with redundant byte swaps cancelling out. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Tony Nguyen <tony.nguyen@bt.com> Message-Id: <911ff31af11922a9afba9b7ce128af8b8b80f316.1566466906.git.tony.nguyen@bt.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
committed by
Richard Henderson
parent
be5c4787e9
commit
9bf825bf3d
@ -1200,38 +1200,6 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
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cpu_loop_exit_atomic(env_cpu(env), retaddr);
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cpu_loop_exit_atomic(env_cpu(env), retaddr);
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}
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}
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#ifdef TARGET_WORDS_BIGENDIAN
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#define NEED_BE_BSWAP 0
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#define NEED_LE_BSWAP 1
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#else
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#define NEED_BE_BSWAP 1
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#define NEED_LE_BSWAP 0
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#endif
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/*
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* Byte Swap Helper
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*
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* This should all dead code away depending on the build host and
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* access type.
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*/
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static inline uint64_t handle_bswap(uint64_t val, MemOp op)
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{
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if ((memop_big_endian(op) && NEED_BE_BSWAP) ||
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(!memop_big_endian(op) && NEED_LE_BSWAP)) {
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switch (op & MO_SIZE) {
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case MO_8: return val;
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case MO_16: return bswap16(val);
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case MO_32: return bswap32(val);
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case MO_64: return bswap64(val);
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default:
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g_assert_not_reached();
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}
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} else {
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return val;
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}
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}
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/*
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/*
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* Load Helpers
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* Load Helpers
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*
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*
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@ -1306,10 +1274,8 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
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}
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}
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}
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}
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/* TODO: Merge bswap into io_readx -> memory_region_dispatch_read. */
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return io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index],
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res = io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index],
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mmu_idx, addr, retaddr, access_type, op);
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mmu_idx, addr, retaddr, access_type, op);
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return handle_bswap(res, op);
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}
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}
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/* Handle slow unaligned access (it spans two pages or IO). */
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/* Handle slow unaligned access (it spans two pages or IO). */
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@ -1552,10 +1518,8 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
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}
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}
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}
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}
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/* TODO: Merge bswap into io_writex -> memory_region_dispatch_write. */
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io_writex(env, &env_tlb(env)->d[mmu_idx].iotlb[index], mmu_idx,
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io_writex(env, &env_tlb(env)->d[mmu_idx].iotlb[index], mmu_idx,
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handle_bswap(val, op),
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val, addr, retaddr, op);
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addr, retaddr, op);
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return;
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return;
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}
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}
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17
exec.c
17
exec.c
@ -3363,14 +3363,9 @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
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l = memory_access_size(mr, l, addr1);
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l = memory_access_size(mr, l, addr1);
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/* XXX: could force current_cpu to NULL to avoid
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/* XXX: could force current_cpu to NULL to avoid
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potential bugs */
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potential bugs */
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val = ldn_p(buf, l);
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val = ldn_he_p(buf, l);
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/*
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* TODO: Merge bswap from ldn_p into memory_region_dispatch_write
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* by using ldn_he_p and dropping MO_TE to get a host-endian value.
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*/
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result |= memory_region_dispatch_write(mr, addr1, val,
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result |= memory_region_dispatch_write(mr, addr1, val,
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size_memop(l) | MO_TE,
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size_memop(l), attrs);
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attrs);
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} else {
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} else {
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/* RAM case */
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/* RAM case */
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ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
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ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
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@ -3431,13 +3426,9 @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
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/* I/O case */
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/* I/O case */
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release_lock |= prepare_mmio_access(mr);
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release_lock |= prepare_mmio_access(mr);
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l = memory_access_size(mr, l, addr1);
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l = memory_access_size(mr, l, addr1);
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/*
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* TODO: Merge bswap from stn_p into memory_region_dispatch_read
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* by using stn_he_p and dropping MO_TE to get a host-endian value.
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*/
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result |= memory_region_dispatch_read(mr, addr1, &val,
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result |= memory_region_dispatch_read(mr, addr1, &val,
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size_memop(l) | MO_TE, attrs);
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size_memop(l), attrs);
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stn_p(buf, l, val);
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stn_he_p(buf, l, val);
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} else {
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} else {
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/* RAM case */
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/* RAM case */
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ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
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ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
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@ -544,16 +544,15 @@ void virtio_address_space_write(VirtIOPCIProxy *proxy, hwaddr addr,
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val = pci_get_byte(buf);
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val = pci_get_byte(buf);
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break;
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break;
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case 2:
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case 2:
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val = cpu_to_le16(pci_get_word(buf));
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val = pci_get_word(buf);
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break;
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break;
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case 4:
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case 4:
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val = cpu_to_le32(pci_get_long(buf));
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val = pci_get_long(buf);
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break;
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break;
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default:
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default:
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/* As length is under guest control, handle illegal values. */
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/* As length is under guest control, handle illegal values. */
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return;
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return;
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}
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}
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/* TODO: Merge bswap from cpu_to_leXX into memory_region_dispatch_write. */
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memory_region_dispatch_write(mr, addr, val, size_memop(len) | MO_LE,
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memory_region_dispatch_write(mr, addr, val, size_memop(len) | MO_LE,
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MEMTXATTRS_UNSPECIFIED);
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MEMTXATTRS_UNSPECIFIED);
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}
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}
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@ -578,7 +577,6 @@ virtio_address_space_read(VirtIOPCIProxy *proxy, hwaddr addr,
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/* Make sure caller aligned buf properly */
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/* Make sure caller aligned buf properly */
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assert(!(((uintptr_t)buf) & (len - 1)));
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assert(!(((uintptr_t)buf) & (len - 1)));
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/* TODO: Merge bswap from leXX_to_cpu into memory_region_dispatch_read. */
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memory_region_dispatch_read(mr, addr, &val, size_memop(len) | MO_LE,
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memory_region_dispatch_read(mr, addr, &val, size_memop(len) | MO_LE,
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MEMTXATTRS_UNSPECIFIED);
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MEMTXATTRS_UNSPECIFIED);
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switch (len) {
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switch (len) {
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@ -586,10 +584,10 @@ virtio_address_space_read(VirtIOPCIProxy *proxy, hwaddr addr,
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pci_set_byte(buf, val);
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pci_set_byte(buf, val);
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break;
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break;
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case 2:
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case 2:
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pci_set_word(buf, le16_to_cpu(val));
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pci_set_word(buf, val);
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break;
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break;
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case 4:
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case 4:
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pci_set_long(buf, le32_to_cpu(val));
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pci_set_long(buf, val);
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break;
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break;
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default:
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default:
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/* As length is under guest control, handle illegal values. */
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/* As length is under guest control, handle illegal values. */
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33
memory.c
33
memory.c
@ -351,32 +351,23 @@ static bool memory_region_big_endian(MemoryRegion *mr)
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#endif
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#endif
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}
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}
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static bool memory_region_wrong_endianness(MemoryRegion *mr)
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static void adjust_endianness(MemoryRegion *mr, uint64_t *data, MemOp op)
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{
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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if ((op & MO_BSWAP) != devend_memop(mr->ops->endianness)) {
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return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
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switch (op & MO_SIZE) {
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#else
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case MO_8:
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return mr->ops->endianness == DEVICE_BIG_ENDIAN;
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#endif
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}
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static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
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{
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if (memory_region_wrong_endianness(mr)) {
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switch (size) {
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case 1:
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break;
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break;
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case 2:
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case MO_16:
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*data = bswap16(*data);
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*data = bswap16(*data);
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break;
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break;
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case 4:
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case MO_32:
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*data = bswap32(*data);
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*data = bswap32(*data);
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break;
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break;
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case 8:
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case MO_64:
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*data = bswap64(*data);
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*data = bswap64(*data);
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break;
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break;
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default:
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default:
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abort();
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g_assert_not_reached();
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}
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}
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}
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}
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}
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}
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@ -1458,7 +1449,7 @@ MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
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}
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}
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r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
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r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
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adjust_endianness(mr, pval, size);
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adjust_endianness(mr, pval, op);
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return r;
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return r;
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}
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}
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@ -1501,7 +1492,7 @@ MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
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return MEMTX_DECODE_ERROR;
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return MEMTX_DECODE_ERROR;
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}
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}
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adjust_endianness(mr, &data, size);
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adjust_endianness(mr, &data, op);
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if ((!kvm_eventfds_enabled()) &&
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if ((!kvm_eventfds_enabled()) &&
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memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
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memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
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@ -2350,7 +2341,7 @@ void memory_region_add_eventfd(MemoryRegion *mr,
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}
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}
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if (size) {
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if (size) {
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adjust_endianness(mr, &mrfd.data, size);
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adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE);
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}
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}
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memory_region_transaction_begin();
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memory_region_transaction_begin();
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for (i = 0; i < mr->ioeventfd_nb; ++i) {
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for (i = 0; i < mr->ioeventfd_nb; ++i) {
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@ -2385,7 +2376,7 @@ void memory_region_del_eventfd(MemoryRegion *mr,
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unsigned i;
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unsigned i;
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if (size) {
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if (size) {
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adjust_endianness(mr, &mrfd.data, size);
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adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE);
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}
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}
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memory_region_transaction_begin();
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memory_region_transaction_begin();
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for (i = 0; i < mr->ioeventfd_nb; ++i) {
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for (i = 0; i < mr->ioeventfd_nb; ++i) {
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@ -38,18 +38,8 @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
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release_lock |= prepare_mmio_access(mr);
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release_lock |= prepare_mmio_access(mr);
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/* I/O case */
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/* I/O case */
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/* TODO: Merge bswap32 into memory_region_dispatch_read. */
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r = memory_region_dispatch_read(mr, addr1, &val,
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r = memory_region_dispatch_read(mr, addr1, &val,
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MO_32 | devend_memop(endian), attrs);
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MO_32 | devend_memop(endian), attrs);
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#if defined(TARGET_WORDS_BIGENDIAN)
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if (endian == DEVICE_LITTLE_ENDIAN) {
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val = bswap32(val);
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}
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#else
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if (endian == DEVICE_BIG_ENDIAN) {
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val = bswap32(val);
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}
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#endif
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} else {
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} else {
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/* RAM case */
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/* RAM case */
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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@ -116,18 +106,8 @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
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release_lock |= prepare_mmio_access(mr);
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release_lock |= prepare_mmio_access(mr);
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/* I/O case */
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/* I/O case */
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/* TODO: Merge bswap64 into memory_region_dispatch_read. */
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r = memory_region_dispatch_read(mr, addr1, &val,
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r = memory_region_dispatch_read(mr, addr1, &val,
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MO_64 | devend_memop(endian), attrs);
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MO_64 | devend_memop(endian), attrs);
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#if defined(TARGET_WORDS_BIGENDIAN)
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if (endian == DEVICE_LITTLE_ENDIAN) {
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val = bswap64(val);
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}
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#else
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if (endian == DEVICE_BIG_ENDIAN) {
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val = bswap64(val);
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}
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#endif
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} else {
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} else {
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/* RAM case */
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/* RAM case */
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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@ -228,18 +208,8 @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
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release_lock |= prepare_mmio_access(mr);
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release_lock |= prepare_mmio_access(mr);
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/* I/O case */
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/* I/O case */
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/* TODO: Merge bswap16 into memory_region_dispatch_read. */
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r = memory_region_dispatch_read(mr, addr1, &val,
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r = memory_region_dispatch_read(mr, addr1, &val,
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MO_16 | devend_memop(endian), attrs);
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MO_16 | devend_memop(endian), attrs);
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#if defined(TARGET_WORDS_BIGENDIAN)
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if (endian == DEVICE_LITTLE_ENDIAN) {
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val = bswap16(val);
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}
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#else
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if (endian == DEVICE_BIG_ENDIAN) {
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val = bswap16(val);
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}
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#endif
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} else {
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} else {
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/* RAM case */
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/* RAM case */
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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@ -342,17 +312,6 @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
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mr = TRANSLATE(addr, &addr1, &l, true, attrs);
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mr = TRANSLATE(addr, &addr1, &l, true, attrs);
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if (l < 4 || !memory_access_is_direct(mr, true)) {
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if (l < 4 || !memory_access_is_direct(mr, true)) {
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release_lock |= prepare_mmio_access(mr);
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release_lock |= prepare_mmio_access(mr);
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#if defined(TARGET_WORDS_BIGENDIAN)
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if (endian == DEVICE_LITTLE_ENDIAN) {
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val = bswap32(val);
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}
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#else
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if (endian == DEVICE_BIG_ENDIAN) {
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val = bswap32(val);
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}
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#endif
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/* TODO: Merge bswap32 into memory_region_dispatch_write. */
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r = memory_region_dispatch_write(mr, addr1, val,
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r = memory_region_dispatch_write(mr, addr1, val,
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MO_32 | devend_memop(endian), attrs);
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MO_32 | devend_memop(endian), attrs);
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} else {
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} else {
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@ -449,17 +408,6 @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
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mr = TRANSLATE(addr, &addr1, &l, true, attrs);
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mr = TRANSLATE(addr, &addr1, &l, true, attrs);
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if (l < 2 || !memory_access_is_direct(mr, true)) {
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if (l < 2 || !memory_access_is_direct(mr, true)) {
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release_lock |= prepare_mmio_access(mr);
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release_lock |= prepare_mmio_access(mr);
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#if defined(TARGET_WORDS_BIGENDIAN)
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if (endian == DEVICE_LITTLE_ENDIAN) {
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val = bswap16(val);
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}
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#else
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|
||||||
if (endian == DEVICE_BIG_ENDIAN) {
|
|
||||||
val = bswap16(val);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
/* TODO: Merge bswap16 into memory_region_dispatch_write. */
|
|
||||||
r = memory_region_dispatch_write(mr, addr1, val,
|
r = memory_region_dispatch_write(mr, addr1, val,
|
||||||
MO_16 | devend_memop(endian), attrs);
|
MO_16 | devend_memop(endian), attrs);
|
||||||
} else {
|
} else {
|
||||||
@ -524,17 +472,6 @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
|
|||||||
mr = TRANSLATE(addr, &addr1, &l, true, attrs);
|
mr = TRANSLATE(addr, &addr1, &l, true, attrs);
|
||||||
if (l < 8 || !memory_access_is_direct(mr, true)) {
|
if (l < 8 || !memory_access_is_direct(mr, true)) {
|
||||||
release_lock |= prepare_mmio_access(mr);
|
release_lock |= prepare_mmio_access(mr);
|
||||||
|
|
||||||
#if defined(TARGET_WORDS_BIGENDIAN)
|
|
||||||
if (endian == DEVICE_LITTLE_ENDIAN) {
|
|
||||||
val = bswap64(val);
|
|
||||||
}
|
|
||||||
#else
|
|
||||||
if (endian == DEVICE_BIG_ENDIAN) {
|
|
||||||
val = bswap64(val);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
/* TODO: Merge bswap64 into memory_region_dispatch_write. */
|
|
||||||
r = memory_region_dispatch_write(mr, addr1, val,
|
r = memory_region_dispatch_write(mr, addr1, val,
|
||||||
MO_64 | devend_memop(endian), attrs);
|
MO_64 | devend_memop(endian), attrs);
|
||||||
} else {
|
} else {
|
||||||
|
Reference in New Issue
Block a user