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Implement missing MIPS supervisor mode bits.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3472 c046a42c-6fe2-441c-8c8c-71466251a162
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ths
2007-10-28 19:45:05 +00:00
parent 8e129e0748
commit 623a930ec3
8 changed files with 51 additions and 37 deletions
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2
cpu-defs.h
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@@ -122,7 +122,7 @@ typedef struct CPUTLBEntry {
written */ \
target_ulong mem_write_vaddr; /* target virtual addr at which the \
memory was written */ \
/* 0 = kernel, 1 = user */ \
/* The meaning of the MMU modes is defined in the target code. */ \
CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
\