mii/qemu
1
0
Fork 0
mirror of https://github.com/mii443/qemu.git synced 2025-08-22 23:25:48 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info

Browse Source 
Pass RISCVCPUConfig as disassemble_info.target_info to support disas
of conflict instructions related to specific extensions.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230523093539.203909-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li
2023-05-23 17:35:34 +08:00
committed by Alistair Francis
parent b902ff2946
commit 454c220100
2 changed files with 8 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
disas/riscv.c
View File

@ -19,7 +19,7 @@
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "disas/dis-asm.h" #include "disas/dis-asm.h"
#include "target/riscv/cpu_cfg.h"
/* types */ /* types */
@ -969,6 +969,7 @@ typedef enum {
/* structures */ /* structures */
typedef struct { typedef struct {
RISCVCPUConfig *cfg;
uint64_t pc; uint64_t pc;
uint64_t inst; uint64_t inst;
int32_t imm; int32_t imm;
@ -4861,11 +4862,13 @@ static void decode_inst_decompress(rv_decode *dec, rv_isa isa)
/* disassemble instruction */ /* disassemble instruction */
static void static void
disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst) disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst,
RISCVCPUConfig *cfg)
{ {
rv_decode dec = { 0 }; rv_decode dec = { 0 };
dec.pc = pc; dec.pc = pc;
dec.inst = inst; dec.inst = inst;
dec.cfg = cfg;
decode_inst_opcode(&dec, isa); decode_inst_opcode(&dec, isa);
decode_inst_operands(&dec, isa); decode_inst_operands(&dec, isa);
decode_inst_decompress(&dec, isa); decode_inst_decompress(&dec, isa);
@ -4920,7 +4923,8 @@ print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa)
break; break;
} }
disasm_inst(buf, sizeof(buf), isa, memaddr, inst); disasm_inst(buf, sizeof(buf), isa, memaddr, inst,
(RISCVCPUConfig *)info->target_info);
(*info->fprintf_func)(info->stream, "%s", buf); (*info->fprintf_func)(info->stream, "%s", buf);
return len; return len;

1
target/riscv/cpu.c
View File

@ -849,6 +849,7 @@ static void riscv_cpu_reset_hold(Object *obj)
static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
{ {
RISCVCPU *cpu = RISCV_CPU(s); RISCVCPU *cpu = RISCV_CPU(s);
info->target_info = &cpu->cfg;
switch (riscv_cpu_mxl(&cpu->env)) { switch (riscv_cpu_mxl(&cpu->env)) {
case MXL_RV32: case MXL_RV32: