mii/qemu
1
0
Fork 0
mirror of https://github.com/mii443/qemu.git synced 2025-08-22 15:15:46 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fix some typos in documentation (most of them found by codespell)

Browse Source 
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Hongren (Zenithal) Zheng <i@zenithal.me>
Message-id: 20220812075642.1200578-1-sw@weilnetz.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Stefan Weil
2022-08-12 09:56:42 +02:00
committed by Peter Maydell
parent 2daf518dd1
commit 120f765e03
4 changed files with 13 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
docs/specs/acpi_erst.rst
View File

@ -108,7 +108,7 @@ Slot 0 contains a backend storage header that identifies the contents
as ERST and also facilitates efficient access to the records.
Depending upon the size of the backend storage, additional slots will
be designated to be a part of the slot 0 header. For example, at 8KiB,
the slot 0 header can accomodate 1021 records. Thus a storage size
the slot 0 header can accommodate 1021 records. Thus a storage size
of 8MiB (8KiB * 1024) requires an additional slot for use by the
header. In this scenario, slot 0 and slot 1 form the backend storage
header, and records can be stored starting at slot 2.
@ -196,5 +196,5 @@ References
[2] "Unified Extensible Firmware Interface Specification",
version 2.1, October 2008.
[3] "Windows Hardware Error Architecture", specfically
[3] "Windows Hardware Error Architecture", specifically
"Error Record Persistence Mechanism".