mirror of
https://github.com/mii443/nel_os.git
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I/O Emulation
This commit is contained in:
Masato Imai
@ -1,5 +1,3 @@
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use core::fmt::Write;
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use lazy_static::lazy_static;
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use spin::Mutex;
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use uart_16550::SerialPort;
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@ -25,19 +23,6 @@ pub fn _print(args: ::core::fmt::Arguments) {
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});
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}
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#[inline(always)]
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pub fn write_byte(byte: u8) {
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use x86_64::instructions::interrupts;
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if interrupts::are_enabled() {
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interrupts::without_interrupts(|| {
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SERIAL1.lock().send(byte);
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});
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} else {
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SERIAL1.lock().send(byte);
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}
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}
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#[macro_export]
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macro_rules! serial_print {
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($($arg:tt)*) => {
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@ -4,7 +4,6 @@ use lazy_static::lazy_static;
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use spin::Mutex;
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use volatile::Volatile;
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use crate::serial::SERIAL1;
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lazy_static! {
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pub static ref WRITER: Mutex<Writer> = Mutex::new(Writer {
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@ -37,15 +36,11 @@ macro_rules! error {
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#[doc(hidden)]
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pub fn _print(args: fmt::Arguments) {
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use core::fmt::Write;
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use x86_64::instructions::interrupts;
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interrupts::without_interrupts(|| {
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//WRITER.lock().write_fmt(args).unwrap();
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SERIAL1
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.lock()
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.write_fmt(args)
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.expect("Printing to serial failed");
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crate::serial::_print(args);
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});
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}
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@ -125,7 +125,7 @@ pub fn handle_cpuid_exit(vcpu: &mut VCpu) {
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pae: true,
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mce: false,
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cx8: true,
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apic: true,
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apic: false,
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_reserved_0: false,
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sep: true,
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mtrr: false,
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134
src/vmm/io.rs
134
src/vmm/io.rs
@ -1,9 +1,4 @@
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use x86::io::inb;
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use crate::{
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serial,
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vmm::{qual::QualIo, vcpu::VCpu},
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};
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use crate::vmm::{qual::QualIo, vcpu::VCpu};
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#[derive(Default)]
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pub struct Serial {
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@ -11,6 +6,36 @@ pub struct Serial {
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pub mcr: u8,
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}
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pub enum InitPhase {
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Uninitialized,
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Phase1,
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Phase2,
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Phase3,
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Initialized,
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}
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pub struct PIC {
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pub primary_mask: u8,
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pub secondary_mask: u8,
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pub primary_phase: InitPhase,
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pub secondary_phase: InitPhase,
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pub primary_base: u8,
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pub secondary_base: u8,
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}
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impl PIC {
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pub fn new() -> Self {
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Self {
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primary_mask: 0xFF,
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secondary_mask: 0xFF,
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primary_phase: InitPhase::Uninitialized,
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secondary_phase: InitPhase::Uninitialized,
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primary_base: 0,
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secondary_base: 0,
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}
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}
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}
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pub fn handle_io(vcpu: &mut VCpu, qual: QualIo) {
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match qual.direction() {
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0 => {
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@ -26,59 +51,82 @@ pub fn handle_io(vcpu: &mut VCpu, qual: QualIo) {
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pub fn handle_io_in(vcpu: &mut VCpu, qual: QualIo) {
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let regs = &mut vcpu.guest_registers;
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match qual.port() {
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0x0CF8..0x0CFF => {
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regs.rax = 0;
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}
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0xC000..0xCFFF => {} //ignore
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0x03F..0x03FF => handle_serial_in(vcpu, qual),
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_ => {
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panic!("IO in: invalid port: {:#x}", qual.port());
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}
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0x0CF8..=0x0CFF => regs.rax = 0,
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0xC000..=0xCFFF => {} //ignore
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0x20..=0x21 => handle_pic_in(vcpu, qual),
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0xA0..=0xA1 => handle_pic_in(vcpu, qual),
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0x0070..=0x0071 => regs.rax = 0,
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_ => regs.rax = 0,
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}
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}
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pub fn handle_io_out(vcpu: &mut VCpu, qual: QualIo) {
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let regs = &vcpu.guest_registers;
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match qual.port() {
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0x0CF8..0x0CFF => {} //ignore
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0xC000..0xCFFF => {} //ignore
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0x03F8..0x03FF => handle_serial_out(vcpu, qual),
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_ => {
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panic!("IO out: invalid port: {:#x}", qual.port());
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}
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0x0CF8..=0x0CFF => {} //ignore
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0xC000..=0xCFFF => {} //ignore
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0x20..=0x21 => handle_pic_out(vcpu, qual),
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0xA0..=0xA1 => handle_pic_out(vcpu, qual),
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0x0070..=0x0071 => {} //ignore
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_ => {}
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}
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}
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fn handle_serial_in(vcpu: &mut VCpu, qual: QualIo) {
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pub fn handle_pic_in(vcpu: &mut VCpu, qual: QualIo) {
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let regs = &mut vcpu.guest_registers;
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match qual.port() {
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0x3F8 => regs.rax = unsafe { inb(qual.port()).into() },
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0x3F9 => regs.rax = vcpu.serial.ier as u64,
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0x3FA => regs.rax = unsafe { inb(qual.port()).into() },
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0x3FB => regs.rax = 0,
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0x3FC => regs.rax = vcpu.serial.mcr as u64,
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0x3FD => regs.rax = unsafe { inb(qual.port()).into() },
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0x3FE => regs.rax = unsafe { inb(qual.port()).into() },
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0x3FF => regs.rax = 0,
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_ => {
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panic!("Serial in: invalid port: {:#x}", qual.port());
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0x21 => match vcpu.pic.primary_phase {
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InitPhase::Uninitialized | InitPhase::Initialized => {
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regs.rax = vcpu.pic.primary_mask as u64;
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}
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_ => {}
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},
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0xA1 => match vcpu.pic.secondary_phase {
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InitPhase::Uninitialized | InitPhase::Initialized => {
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regs.rax = vcpu.pic.secondary_mask as u64;
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}
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_ => {}
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},
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_ => {}
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}
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}
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fn handle_serial_out(vcpu: &mut VCpu, qual: QualIo) {
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pub fn handle_pic_out(vcpu: &mut VCpu, qual: QualIo) {
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let regs = &mut vcpu.guest_registers;
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let pic = &mut vcpu.pic;
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let dx = regs.rax as u8;
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match qual.port() {
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0x3F8 => serial::write_byte(regs.rax as u8),
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0x3F9 => vcpu.serial.ier = regs.rax as u8,
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0x3FA => {}
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0x3FB => {}
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0x3FC => vcpu.serial.mcr = regs.rax as u8,
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0x3FD => {}
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0x3FF => {}
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_ => {
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panic!("Serial out: invalid port: {:#x}", qual.port());
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0x20 => match dx {
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0x11 => pic.primary_phase = InitPhase::Phase1,
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0x60..=0x67 => {}
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_ => panic!("Primary PIC command: {:#x}", dx),
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},
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0x21 => match pic.primary_phase {
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InitPhase::Uninitialized | InitPhase::Initialized => pic.primary_mask = dx,
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InitPhase::Phase1 => {
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pic.primary_base = dx;
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pic.primary_phase = InitPhase::Phase2;
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}
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InitPhase::Phase2 => {
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pic.primary_phase = InitPhase::Phase3;
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}
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InitPhase::Phase3 => pic.primary_phase = InitPhase::Initialized,
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},
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0xA0 => match dx {
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0x11 => pic.secondary_phase = InitPhase::Phase1,
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0x60..=0x67 => {}
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_ => panic!("Secondary PIC command: {:#x}", dx),
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},
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0xA1 => match pic.secondary_phase {
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InitPhase::Uninitialized | InitPhase::Initialized => pic.secondary_mask = dx,
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InitPhase::Phase1 => {
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pic.secondary_base = dx;
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pic.secondary_phase = InitPhase::Phase2;
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}
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InitPhase::Phase2 => {
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pic.secondary_phase = InitPhase::Phase3;
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}
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InitPhase::Phase3 => pic.secondary_phase = InitPhase::Initialized,
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},
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_ => {}
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}
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}
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100
src/vmm/vcpu.rs
100
src/vmm/vcpu.rs
@ -1,6 +1,7 @@
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use core::{
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arch::x86_64::{_xgetbv, _xsetbv},
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u64,
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convert::TryInto,
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u64, u8,
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};
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use x86::{
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@ -10,20 +11,24 @@ use x86::{
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msr::{rdmsr, IA32_EFER, IA32_FS_BASE},
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vmx::{vmcs, VmFail},
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};
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use x86_64::{registers::control::Cr4Flags, structures::paging::OffsetPageTable, VirtAddr};
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use x86_64::{
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registers::control::Cr4Flags,
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structures::paging::{FrameAllocator, OffsetPageTable},
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VirtAddr,
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};
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use crate::{
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info,
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memory::BootInfoFrameAllocator,
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vmm::{
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cpuid, cr, fpu,
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io::{self, Serial},
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io::{self, Serial, PIC},
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msr,
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qual::{QualCr, QualIo},
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vmcs::{
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DescriptorType, EntryControls, Granularity, PrimaryExitControls,
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PrimaryProcessorBasedVmExecutionControls, SecondaryProcessorBasedVmExecutionControls,
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SegmentRights, VmxExitInfo, VmxExitReason,
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SegmentRights, VmxExitReason,
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},
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},
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};
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@ -53,6 +58,9 @@ pub struct VCpu {
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pub xcr0: XCR0,
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pub host_xcr0: u64,
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pub serial: Serial,
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pub io_bitmap_a: x86_64::structures::paging::PhysFrame,
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pub io_bitmap_b: x86_64::structures::paging::PhysFrame,
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pub pic: PIC,
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}
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const TEMP_STACK_SIZE: usize = 4096;
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@ -66,6 +74,10 @@ impl VCpu {
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let ept = EPT::new(frame_allocator);
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let eptp = EPTP::new(&ept.root_table);
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// Allocate I/O bitmaps (4KB each)
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let io_bitmap_a = frame_allocator.allocate_frame().unwrap();
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let io_bitmap_b = frame_allocator.allocate_frame().unwrap();
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VCpu {
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vmxon,
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vmcs,
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@ -80,6 +92,9 @@ impl VCpu {
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xcr0: XCR0(3),
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host_xcr0: 0,
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serial: Serial::default(),
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io_bitmap_a,
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io_bitmap_b,
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pic: PIC::new(),
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}
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}
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@ -99,6 +114,7 @@ impl VCpu {
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self.setup_exit_ctrls().unwrap();
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self.setup_host_state().unwrap();
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self.setup_guest_state().unwrap();
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self.setup_io_bitmaps();
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self.setup_guest_memory(frame_allocator);
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self.register_msrs(&mapper);
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}
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@ -304,11 +320,12 @@ impl VCpu {
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primary_exec_ctrl.0 |= (reserved_bits & 0xFFFFFFFF) as u32;
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primary_exec_ctrl.0 &= (reserved_bits >> 32) as u32;
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primary_exec_ctrl.set_hlt(false);
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primary_exec_ctrl.set_hlt(true);
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primary_exec_ctrl.set_activate_secondary_controls(true);
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primary_exec_ctrl.set_use_tpr_shadow(true);
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primary_exec_ctrl.set_use_msr_bitmap(false);
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primary_exec_ctrl.set_unconditional_io(true);
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primary_exec_ctrl.set_unconditional_io(false);
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primary_exec_ctrl.set_use_io_bitmap(true);
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primary_exec_ctrl.write();
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@ -395,6 +412,59 @@ impl VCpu {
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Ok(())
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}
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pub fn setup_io_bitmaps(&mut self) {
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info!("Setting up I/O bitmaps");
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let bitmap_a_vaddr = self.io_bitmap_a.start_address().as_u64() + self.phys_mem_offset;
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let bitmap_b_vaddr = self.io_bitmap_b.start_address().as_u64() + self.phys_mem_offset;
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unsafe {
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core::ptr::write_bytes(bitmap_a_vaddr as *mut u8, u8::MAX, 4096);
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core::ptr::write_bytes(bitmap_b_vaddr as *mut u8, u8::MAX, 4096);
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}
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let bitmap_a = unsafe { core::slice::from_raw_parts_mut(bitmap_a_vaddr as *mut u8, 4096) };
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let bitmap_b = unsafe { core::slice::from_raw_parts_mut(bitmap_b_vaddr as *mut u8, 4096) };
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self.set_io_ports(bitmap_a, bitmap_b, 0x02F8..=0x03FF);
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self.set_io_ports(bitmap_a, bitmap_b, 0x0040..=0x0047);
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unsafe {
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vmwrite(
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vmcs::control::IO_BITMAP_A_ADDR_FULL,
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self.io_bitmap_a.start_address().as_u64(),
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)
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.unwrap();
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vmwrite(
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vmcs::control::IO_BITMAP_B_ADDR_FULL,
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self.io_bitmap_b.start_address().as_u64(),
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)
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.unwrap();
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}
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info!("I/O bitmaps configured - PCI ports 0xC000-0xCFFF will trigger VM exits");
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}
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fn set_io_ports(
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&self,
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bitmap_a: &mut [u8],
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bitmap_b: &mut [u8],
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ports: core::ops::RangeInclusive<u16>,
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) {
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for port in ports {
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if port <= 0x7FFF {
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let byte_index = port as usize / 8;
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let bit_index = port as usize % 8;
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bitmap_a[byte_index] &= !(1 << bit_index);
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} else {
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let adjusted_port = port - 0x8000;
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let byte_index = adjusted_port as usize / 8;
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let bit_index = adjusted_port as usize % 8;
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bitmap_b[byte_index] &= !(1 << bit_index);
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}
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}
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}
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pub fn setup_host_state(&mut self) -> Result<(), VmFail> {
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info!("Setting up host state");
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unsafe {
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@ -681,10 +751,11 @@ impl VCpu {
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}
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fn vmexit_handler(&mut self) {
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let info = VmxExitInfo::read();
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let exit_reason_raw = unsafe { vmread(vmcs::ro::EXIT_REASON).unwrap() as u32 };
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if info.entry_failure() {
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let reason = info.0 & 0xFF;
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if (exit_reason_raw & (1 << 31)) != 0 {
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// VM-entry failure
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let reason = exit_reason_raw & 0xFF;
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match reason {
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33 => {
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info!(" Reason: VM-entry failure due to invalid guest state");
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@ -698,7 +769,9 @@ impl VCpu {
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_ => {}
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}
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} else {
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match info.get_reason() {
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let basic_reason = (exit_reason_raw & 0xFFFF) as u16;
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let exit_reason: VmxExitReason = basic_reason.try_into().unwrap();
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match exit_reason {
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VmxExitReason::HLT => {
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info!("HLT instruction executed");
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}
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@ -734,12 +807,13 @@ impl VCpu {
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}
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VmxExitReason::IO_INSTRUCTION => {
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let qual = unsafe { vmread(vmcs::ro::EXIT_QUALIFICATION).unwrap() };
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let qual = QualIo(qual);
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io::handle_io(self, qual);
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let qual_io = QualIo(qual);
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io::handle_io(self, qual_io);
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self.step_next_inst().unwrap();
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}
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_ => {
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panic!("VMExit reason: {:?}", info.get_reason());
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panic!("VMExit reason: {:?}", exit_reason);
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}
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}
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}
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