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MDIO/impl/pnr/MDIO.timing_paths
mii 9b2e5fcdb2 wip
2023-06-18 20:56:17 +09:00

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=====
SETUP
4.809
5.970
10.779
cnt_14_s1
0.814
1.046
n710_s29
1.623
2.140
n710_s23
2.554
2.925
n709_s24
3.618
4.071
n709_s29
4.885
5.256
n709_s28
5.508
5.970
cnt_2_s1
5.970
=====
SETUP
4.892
5.887
10.779
cnt_14_s1
0.814
1.046
n710_s29
1.623
2.140
n710_s23
2.554
2.925
n714_s24
3.629
4.082
n714_s22
4.766
5.315
n714_s18
5.317
5.887
state_1_s1
5.887
=====
SETUP
5.007
5.772
10.779
cnt_14_s1
0.814
1.046
n710_s29
1.623
2.140
n710_s23
2.554
2.925
n714_s24
3.629
4.082
n715_s24
4.738
5.200
n715_s21
5.202
5.772
state_0_s1
5.772
=====
SETUP
5.025
5.754
10.779
cnt_3_s1
0.814
1.046
n705_s22
1.541
1.994
n698_s22
2.256
2.773
n683_s22
3.228
3.681
n680_s22
4.128
4.683
n681_s21
5.184
5.754
cnt_30_s1
5.754
=====
SETUP
5.025
5.754
10.779
cnt_3_s1
0.814
1.046
n705_s22
1.541
1.994
n698_s22
2.256
2.773
n683_s22
3.228
3.681
n680_s22
4.128
4.683
n680_s21
5.184
5.754
cnt_31_s1
5.754
=====
SETUP
5.052
5.727
10.779
cnt_14_s1
0.814
1.046
n710_s29
1.623
2.140
n710_s23
2.554
2.925
n709_s24
3.618
4.071
n709_s29
4.885
5.256
n711_s21
5.265
5.727
cnt_0_s1
5.727
=====
SETUP
5.229
5.549
10.779
cnt_3_s1
0.814
1.046
n705_s22
1.541
1.994
n698_s22
2.256
2.773
n683_s22
3.228
3.681
n680_s22
4.128
4.683
n682_s21
5.178
5.549
cnt_29_s1
5.549
=====
SETUP
5.267
5.512
10.779
cnt_14_s1
0.814
1.046
n710_s29
1.623
2.140
n710_s23
2.554
2.925
n706_s23
3.618
3.989
n706_s22
4.164
4.535
n707_s21
4.963
5.512
cnt_4_s1
5.512
=====
SETUP
5.267
5.512
10.779
cnt_14_s1
0.814
1.046
n710_s29
1.623
2.140
n710_s23
2.554
2.925
n706_s23
3.618
3.989
n706_s22
4.164
4.535
n706_s21
4.963
5.512
cnt_5_s1
5.512
=====
SETUP
5.296
5.595
10.891
CLK_ibuf
0.000
0.683
uart/clock_count_31_s0
0.926
1.158
uart/n12_s6
1.816
2.371
uart/n12_s1
3.027
3.398
uart/send_count_3_s6
3.407
3.860
uart/n204_s10
4.048
4.603
uart/n206_s8
5.025
5.595
uart/send_count_2_s2
5.595
=====
SETUP
5.317
5.574
10.891
CLK_ibuf
0.000
0.683
uart/clock_count_31_s0
0.926
1.158
uart/n12_s6
1.816
2.371
uart/n12_s1
3.027
3.398
uart/send_count_3_s6
3.407
3.860
uart/n204_s10
4.048
4.603
uart/n204_s8
5.025
5.574
uart/send_count_3_s2
5.574
=====
SETUP
5.549
5.342
10.891
CLK_ibuf
0.000
0.683
uart/clock_count_31_s0
0.926
1.158
uart/n12_s6
1.816
2.371
uart/n12_s1
3.027
3.398
uart/send_count_3_s6
3.407
3.860
uart/n204_s10
4.048
4.618
uart/n210_s8
4.793
5.342
uart/send_count_0_s2
5.342
=====
SETUP
5.582
5.197
10.779
cnt_14_s1
0.814
1.046
n710_s29
1.623
2.140
n710_s23
2.554
2.925
n706_s23
3.618
3.989
n713_s23
4.164
4.626
n713_s22
4.627
5.197
state_2_s0
5.197
=====
SETUP
5.676
5.215
10.891
CLK_ibuf
0.000
0.683
uart/clock_count_31_s0
0.926
1.158
uart/n12_s6
1.816
2.371
uart/n12_s1
3.027
3.398
uart/send_count_3_s6
3.407
3.860
uart/send_count_3_s4
4.287
4.857
uart/send_count_0_s2
5.215
=====
SETUP
5.676
5.215
10.891
CLK_ibuf
0.000
0.683
uart/clock_count_31_s0
0.926
1.158
uart/n12_s6
1.816
2.371
uart/n12_s1
3.027
3.398
uart/send_count_3_s6
3.407
3.860
uart/send_count_3_s4
4.287
4.857
uart/send_count_1_s2
5.215
=====
SETUP
5.699
5.192
10.891
CLK_ibuf
0.000
0.683
uart/clock_count_31_s0
0.926
1.158
uart/n12_s6
1.816
2.371
uart/n12_s1
3.027
3.398
uart/send_count_3_s6
3.407
3.860
uart/send_count_3_s4
4.287
4.857
uart/send_count_2_s2
5.192
=====
SETUP
5.699
5.192
10.891
CLK_ibuf
0.000
0.683
uart/clock_count_31_s0
0.926
1.158
uart/n12_s6
1.816
2.371
uart/n12_s1
3.027
3.398
uart/send_count_3_s6
3.407
3.860
uart/send_count_3_s4
4.287
4.857
uart/send_count_3_s2
5.192
=====
SETUP
5.727
5.164
10.891
CLK_ibuf
0.000
0.683
uart/clock_count_31_s0
0.926
1.158
uart/n12_s6
1.816
2.371
uart/n12_s1
3.027
3.398
uart/send_count_3_s6
3.407
3.860
uart/n204_s10
4.048
4.618
uart/n208_s8
4.793
5.164
uart/send_count_1_s2
5.164
=====
SETUP
5.752
5.027
10.779
cnt_14_s1
0.814
1.046
n710_s29
1.623
2.140
n710_s23
2.554
2.925
n712_s28
3.452
3.905
n712_s21
4.565
5.027
state_3_s1
5.027
=====
SETUP
5.959
4.820
10.779
cnt_14_s1
0.814
1.046
n710_s29
1.623
2.140
n710_s23
2.554
2.925
n710_s22
3.629
4.082
n710_s21
4.271
4.820
cnt_1_s1
4.820
=====
SETUP
5.982
4.797
10.779
cnt_3_s1
0.814
1.046
n705_s22
1.541
1.994
n698_s22
2.256
2.773
n688_s24
3.246
3.801
n690_s21
4.227
4.797
cnt_21_s1
4.797
=====
SETUP
6.006
4.885
10.891
CLK_ibuf
0.000
0.683
uart/clock_count_31_s0
0.926
1.158
uart/n12_s6
1.816
2.371
uart/n12_s1
3.027
3.398
uart/send_count_3_s6
3.407
3.860
uart/n185_s12
4.048
4.419
uart/n185_s10
4.423
4.885
uart/tx_reg_s2
4.885
=====
SETUP
6.034
4.857
10.891
CLK_ibuf
0.000
0.683
uart/clock_count_31_s0
0.926
1.158
uart/n12_s6
1.816
2.371
uart/n12_s1
3.027
3.398
uart/send_count_3_s6
3.407
3.860
uart/n194_s10
4.287
4.857
uart/state_0_s1
4.857
=====
SETUP
6.081
4.698
10.779
cnt_3_s1
0.814
1.046
n705_s22
1.541
1.994
n698_s22
2.256
2.773
n683_s22
3.228
3.681
n684_s21
4.128
4.698
cnt_27_s1
4.698
=====
SETUP
6.081
4.698
10.779
cnt_3_s1
0.814
1.046
n705_s22
1.541
1.994
n698_s22
2.256
2.773
n683_s22
3.228
3.681
n683_s21
4.128
4.698
cnt_28_s1
4.698
=====
HOLD
-0.054
0.852
0.906
mdc_cnt_0_s0
0.852
=====
HOLD
-0.051
0.855
0.906
mdc_cnt_1_s0
0.855
=====
HOLD
-0.051
0.855
0.906
mdc_cnt_2_s0
0.855
=====
HOLD
-0.051
0.855
0.906
mdc_cnt_3_s0
0.855
=====
HOLD
-0.051
0.855
0.906
mdc_cnt_4_s0
0.855
=====
HOLD
0.425
1.296
0.871
CLK_ibuf
0.000
0.675
uart/send_count_3_s2
0.860
1.062
uart/n204_s8
1.064
1.296
uart/send_count_3_s2
1.296
=====
HOLD
0.425
1.296
0.871
CLK_ibuf
0.000
0.675
uart/clock_count_2_s0
0.860
1.062
uart/n44_s
1.064
1.296
uart/clock_count_2_s0
1.296
=====
HOLD
0.425
1.296
0.871
CLK_ibuf
0.000
0.675
uart/clock_count_8_s0
0.860
1.062
uart/n38_s
1.064
1.296
uart/clock_count_8_s0
1.296
=====
HOLD
0.425
1.296
0.871
CLK_ibuf
0.000
0.675
uart/clock_count_12_s0
0.860
1.062
uart/n34_s
1.064
1.296
uart/clock_count_12_s0
1.296
=====
HOLD
0.425
1.296
0.871
CLK_ibuf
0.000
0.675
uart/clock_count_14_s0
0.860
1.062
uart/n32_s
1.064
1.296
uart/clock_count_14_s0
1.296
=====
HOLD
0.425
1.296
0.871
CLK_ibuf
0.000
0.675
uart/clock_count_18_s0
0.860
1.062
uart/n28_s
1.064
1.296
uart/clock_count_18_s0
1.296
=====
HOLD
0.425
1.296
0.871
CLK_ibuf
0.000
0.675
uart/clock_count_20_s0
0.860
1.062
uart/n26_s
1.064
1.296
uart/clock_count_20_s0
1.296
=====
HOLD
0.425
1.296
0.871
CLK_ibuf
0.000
0.675
uart/clock_count_24_s0
0.860
1.062
uart/n22_s
1.064
1.296
uart/clock_count_24_s0
1.296
=====
HOLD
0.425
1.296
0.871
CLK_ibuf
0.000
0.675
uart/clock_count_26_s0
0.860
1.062
uart/n20_s
1.064
1.296
uart/clock_count_26_s0
1.296
=====
HOLD
0.425
1.296
0.871
CLK_ibuf
0.000
0.675
uart/clock_count_30_s0
0.860
1.062
uart/n16_s
1.064
1.296
uart/clock_count_30_s0
1.296
=====
HOLD
0.425
1.296
0.871
CLK_ibuf
0.000
0.675
mdc_cnt_0_s0
0.860
1.062
n97_s2
1.064
1.296
mdc_cnt_0_s0
1.296
=====
HOLD
0.425
1.296
0.871
CLK_ibuf
0.000
0.675
mdc_cnt_3_s0
0.860
1.062
n94_s
1.064
1.296
mdc_cnt_3_s0
1.296
=====
HOLD
0.425
1.296
0.871
RMII_CLK_ibuf
0.000
0.675
reg_led_3_s0
0.860
1.062
n50_s0
1.064
1.296
reg_led_3_s0
1.296
=====
HOLD
0.425
1.029
0.604
cnt_10_s1
0.593
0.795
n701_s21
0.797
1.029
cnt_10_s1
1.029
=====
HOLD
0.425
1.029
0.604
cnt_24_s1
0.593
0.795
n687_s21
0.797
1.029
cnt_24_s1
1.029
=====
HOLD
0.425
1.029
0.604
cnt_31_s1
0.593
0.795
n680_s21
0.797
1.029
cnt_31_s1
1.029
=====
HOLD
0.427
1.297
0.871
CLK_ibuf
0.000
0.675
uart/send_count_2_s2
0.860
1.062
uart/n206_s8
1.065
1.297
uart/send_count_2_s2
1.297
=====
HOLD
0.427
1.297
0.871
CLK_ibuf
0.000
0.675
uart/clock_count_0_s0
0.860
1.062
uart/n46_s2
1.065
1.297
uart/clock_count_0_s0
1.297
=====
HOLD
0.427
1.297
0.871
CLK_ibuf
0.000
0.675
uart/clock_count_6_s0
0.860
1.062
uart/n40_s
1.065
1.297
uart/clock_count_6_s0
1.297
=====
HOLD
0.427
1.030
0.604
cnt_3_s1
0.593
0.795
n708_s23
0.798
1.030
cnt_3_s1
1.030
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